Power-constrained Testing of VLSI Circuits [electronic resource] /

Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density. Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.

Bibliographic Details

Main Authors:	Nicolici, Nicola. author., Al-Hashimi, Bashir M. author., SpringerLink (Online service)
Format:	Texto biblioteca
Language:	eng
Published:	Boston, MA : Springer US, 2003
Subjects:	Engineering., Computer-aided engineering., Electrical engineering., Electronic circuits., Circuits and Systems., Electrical Engineering., Computer-Aided Engineering (CAD, CAE) and Design.,
Online Access:	http://dx.doi.org/10.1007/b105922
Tags:	Add Tag No Tags, Be the first to tag this record!