![Advances in Computer Systems Architecture [electronic resource] : 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004. Proceedings /](/search/themes/bootstrap3/images/libros.png)
Advances in Computer Systems Architecture [electronic resource] : 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004. Proceedings /
On behalf of the program committee, we were pleased to present this year’s program for ACSAC: Asia-Paci?c Computer Systems Architecture Conference. Now in its ninth year, ACSAC continues to provide an excellent forum for researchers, educators and practitioners to come to the Asia-Paci?c region to exchange ideas on the latest developments in computer systems architecture. This year, the paper submission and review processes were semiautomated using the free version of CyberChair. We received 152 submissions, the largest number ever.Eachpaperwasassignedatleastthree,mostlyfour,andinafewcaseseven ?ve committee members for review. All of the papers were reviewed in a t- monthperiod,duringwhichtheprogramchairsregularlymonitoredtheprogress of the review process. When reviewers claimed inadequate expertise, additional reviewers were solicited. In the end, we received a total of 594 reviews (3.9 per paper) from committee members as well as 248 coreviewers whose names are acknowledged in the proceedings. We would like to thank all of them for their time and e?ort in providing us with such timely and high-quality reviews, some of them on extremely short notice.
| Auteurs principaux: | , , |
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| Format: | Texto biblioteca |
| Langue: | eng |
| Publié: |
Berlin, Heidelberg : Springer Berlin Heidelberg,
2004
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| Sujets: | Computer science., Arithmetic and logic units, Computer., Input-output equipment (Computers)., Microprocessors., Computer communication systems., Architecture, Computer., Computer Science., Computer System Implementation., Arithmetic and Logic Structures., Input/Output and Data Communications., Register-Transfer-Level Implementation., Computer Communication Networks., Processor Architectures., |
| Accès en ligne: | http://dx.doi.org/10.1007/b100354 |
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